Daniel Morgan

I research semiconductor lithography materials, with a particular focus on photoresists and the materials required to create increasingly precise semiconductor patterns. My work examines material performance, process requirements, advanced lithography, and the relationship between materials innovation and semiconductor scaling. I publish on this website because lithography materials play a critical role in determining how successfully manufacturers can transfer increasingly complex patterns onto semiconductor wafers. As process dimensions become smaller, material properties and process control become increasingly important. My research follows photoresist technologies, advanced patterning requirements, process compatibility, material performance, and the evolution of lithography techniques used in leading-edge manufacturing. I also examine how new semiconductor architectures create additional material challenges. I monitor developments across logic, memory, and advanced packaging applications and study how material suppliers respond to increasingly demanding process specifications. My goal is to make semiconductor materials easier to understand by connecting chemistry, lithography processes, manufacturing requirements, and industry investment.

Research Field

Materials analyst specializing in photoresists, lithography materials, advanced patterning, process compatibility, and materials innovation for leading-edge semiconductors.

Introduction

Daniel Morgan is a semiconductor materials researcher specializing in photoresists and lithography-related materials. His work examines the material technologies required to create increasingly precise patterns during semiconductor manufacturing.

Daniel studies photoresist performance, advanced patterning, process compatibility, material properties, and the challenges created by increasingly complex semiconductor architectures. His coverage spans leading-edge logic, memory, and related manufacturing applications.

As semiconductor geometries become more demanding, lithography materials must meet increasingly strict requirements for resolution, uniformity, sensitivity, and process stability. Daniel follows how material suppliers respond to these requirements through new formulations and technologies.

His research connects materials science with semiconductor manufacturing economics. Through his articles, Daniel explains how developments in lithography materials can influence process capability, technology transitions, and the broader semiconductor materials supply chain.

Silicon Wafer Shipment Area Growth: The 2026 Recovery Trajectory

The silicon wafer market is recovering in 2026, but the recovery is neither uniform nor adequately explained by the artificial intelligence investment boom alone. Shipment area is increasing, advanced applications remain the strongest demand engine, and industrial and automotive markets are showing signs of improvement. Yet rising volumes do not automatically imply stronger pricing, fully utilized factories, or an equally healthy outlook across wafer categories.

Compilation Differences and Tracking Choices Between CSI All-Share Semi and CES Semi Indices

When investors compare China’s semiconductor indicators, the first instinct is often to ask which one is “better.” But that question is usually too simple. A more useful question is: what exactly is each index trying to capture, how is it built, and what does that mean for tracking choice? The CSI All Share Semi indicator and the CES Semi indicator may seem to point at the same industry, but they can behave quite differently because of the way they are compiled, weighted, and rebalanced. Those differences matter, especially for investors who want semiconductor exposure that is either broader, purer, more liquid, or more representative of the domestic ecosystem.

Soaring Demand for SOI Substrates in RF and Power Devices

Silicon-on-insulator (SOI) technology has moved from a niche substrate option to a strategic pillar in modern semiconductor design, particularly for radio-frequency (RF) and power devices. As smartphones, 5G infrastructure, connected vehicles, and advanced power management systems proliferate, the performance and integration demands placed on RF front-ends and power stages have intensified. SOI substrates, with their unique electrical and isolation characteristics, are increasingly seen as the ideal foundation for meeting these requirements. The result is a pronounced surge in demand for SOI across multiple device categories and applications.

D2D Interface Bandwidth and Latency Comparison in Chiplet Architectures

Chiplet architecture has turned the package into a real performance battleground. Once multiple dies are placed side by side or stacked within the same advanced package, the quality of the die-to-die, or D2D, interface becomes one of the most important determinants of system behavior. Bandwidth is no longer a nice-to-have metric, and latency is no longer a small implementation detail. Together, they shape whether a chiplet system feels nearly monolithic or frustratingly fragmented.